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	<id>https://wiki.cs.auckland.ac.nz/stageonewiki/api.php?action=feedcontributions&amp;feedformat=atom&amp;user=Jwu550</id>
	<title>Stage One Wiki - User contributions [en]</title>
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	<updated>2026-06-25T14:45:00Z</updated>
	<subtitle>User contributions</subtitle>
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	<entry>
		<id>https://wiki.cs.auckland.ac.nz/stageonewiki/index.php?title=User:Jwu550&amp;diff=38504</id>
		<title>User:Jwu550</title>
		<link rel="alternate" type="text/html" href="https://wiki.cs.auckland.ac.nz/stageonewiki/index.php?title=User:Jwu550&amp;diff=38504"/>
		<updated>2015-08-02T11:38:24Z</updated>

		<summary type="html">&lt;p&gt;Jwu550: Final Revision&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;Welcome to the test Wiki page created by user: jwu550. &lt;br /&gt;
&lt;br /&gt;
I decided to do a Wiki page on the upcoming Intel Skylake CPU instead, the wait is almost over :D&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;&#039;&#039; DISCLAIMER: The following information was borrowed from Wikipedia.com for design testing purpose only. &#039;&#039;&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
= Skylake (microarchitecture) =&lt;br /&gt;
&lt;br /&gt;
Skylake is the codename used by Intel for a processor microarchitecture under development and due to launch in 2015 as the successor to the Broadwell microarchitecture.Skylake is a microarchitecture redesign using an already existing process technology, serving as a &amp;quot;tock&amp;quot; in the Intel&#039;s &amp;quot;tick-tock&amp;quot; manufacturing and design model. According to Intel, the redesign brings greater CPU and GPU performance and reduced power consumption. Skylake will use the same 14 nm manufacturing process as Broadwell despite the expectancy of the manufacturing process&#039; transition to 10 nm in 2017 following the Skylake&#039;s &amp;quot;tick&amp;quot; step in the tick-tock release cycle; the codename for this 10 nm die shrink is Cannonlake.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Features ==&lt;br /&gt;
&lt;br /&gt;
Like its predecessor, Broadwell, Skylake is expected to become initially available in four variants, identified by the suffixes &amp;quot;S&amp;quot; (SKL-S), &amp;quot;H&amp;quot; (SKL-H), &amp;quot;U&amp;quot; (SKL-U), and &amp;quot;Y&amp;quot; (SKL-Y). An overclockable &amp;quot;K&amp;quot; variant with unlocked multipliers is expected to launch at the same time. The H, U and Y variants will be manufactured in ball grid array (BGA) packaging, while the S variant will be manufactured in land grid array (LGA) packaging using a new socket, LGA 1151. Skylake will be used in conjunction with Intel 100 Series chipsets, also known as Sunrise Point.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
=== Architecture ===&lt;br /&gt;
*14 nm manufacturing process&lt;br /&gt;
*LGA 1151 socket&lt;br /&gt;
*Z170/H170 chipset (Sunrise Point)&lt;br /&gt;
*Thermal design power (TDP) up to 95 W (LGA 1151)&lt;br /&gt;
*Support for both DDR3 SDRAM and DDR4 SDRAM in mainstream variants, using custom UniDIMM SO-DIMM form factor with up to 64 GB of RAM on LGA 1151 variants.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
==== See also ====&lt;br /&gt;
#[[List of Intel CPU microarchitectures |List of Intel CPU microarchitectures]]&lt;br /&gt;
#[https://en.wikipedia.org/wiki/DDR3_SDRAM DDR3 SDRAM]&lt;br /&gt;
#[https://en.wikipedia.org/wiki/DDR4_SDRAM DDR4 SDRAM]&lt;/div&gt;</summary>
		<author><name>Jwu550</name></author>
	</entry>
	<entry>
		<id>https://wiki.cs.auckland.ac.nz/stageonewiki/index.php?title=List_of_Intel_CPU_microarchitectures&amp;diff=38503</id>
		<title>List of Intel CPU microarchitectures</title>
		<link rel="alternate" type="text/html" href="https://wiki.cs.auckland.ac.nz/stageonewiki/index.php?title=List_of_Intel_CPU_microarchitectures&amp;diff=38503"/>
		<updated>2015-08-02T11:33:38Z</updated>

		<summary type="html">&lt;p&gt;Jwu550: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;&#039;&#039;&#039;The following is a partial list of Intel CPU microarchitectures. The list is not complete.&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
===x86 microarchitectures===&lt;br /&gt;
*8086: first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80.&lt;br /&gt;
*186: included a DMA controller, interrupt controller, timers, and chip select logic.&lt;br /&gt;
*286: first x86 processor with protected mode&lt;br /&gt;
*i386: first 32-bit x86 processor&lt;br /&gt;
*i486: Intel&#039;s second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining.&lt;br /&gt;
*P5: original Pentium microprocessors&lt;br /&gt;
*P6: used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. Pentium M: updated version of Pentium III&#039;s P6 microarchitecture designed from the ground up for mobile computing.&lt;br /&gt;
*Enhanced Pentium M: updated, dual core version of the Pentium M microarchitecture used in Core microprocessors.&lt;br /&gt;
 &lt;br /&gt;
*NetBurst: used in Pentium 4, Pentium D, and some Xeon microprocessors. Commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Later revisions were the first to feature Intel&#039;s x86-64 architecture.&lt;br /&gt;
*Core: reengineered P6-based microarchitecture used in Core 2 and Xeon microprocessors, built on a 65 nm process. Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, and SSE4.1 instructions.&lt;br /&gt;
 &lt;br /&gt;
*Nehalem: released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.&lt;br /&gt;
 &lt;br /&gt;
*Sandy Bridge: released January 9, 2011, built on a 32 nm process and used in the Core i7, Core i5, Core i3 second generation microprocessors, and in Pentium B9XX and Celeron B8XX series. Formerly called Gesher but renamed in 2007.[1] Ivy Bridge: 22 nm shrink of the Sandy Bridge microarchitecture released April 28, 2012.&lt;br /&gt;
 &lt;br /&gt;
*Haswell: new 22 nm microarchitecture, released June 3, 2013. Broadwell: 14 nm shrink of the Haswell microarchitecture, released in September 2014. Formerly called Rockwell.&lt;br /&gt;
 &lt;br /&gt;
*Skylake: future Intel microarchitecture, based on a 14 nm process. Kaby Lake: expected in 2016&lt;br /&gt;
*Cannonlake: 10 nm shrink of the Skylake microarchitecture. Formerly called Skymont.&lt;br /&gt;
 &lt;br /&gt;
*Larrabee: multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called MIC (Many Integrated Core).&lt;br /&gt;
*Bonnell: 45 nm, low-power, in-order microarchitecture for use in Atom processors. Saltwell: 32 nm shrink of the Bonnell microarchitecture.&lt;br /&gt;
 &lt;br /&gt;
*Silvermont: 22 nm, out-of-order microarchitecture for use in Atom processors. Airmont: 14 nm shrink of the Silvermont microarchitecture.&lt;br /&gt;
 &lt;br /&gt;
*Goldmont: 14 nm Atom microarchitecture.&lt;/div&gt;</summary>
		<author><name>Jwu550</name></author>
	</entry>
	<entry>
		<id>https://wiki.cs.auckland.ac.nz/stageonewiki/index.php?title=List_of_Intel_CPU_microarchitectures&amp;diff=38502</id>
		<title>List of Intel CPU microarchitectures</title>
		<link rel="alternate" type="text/html" href="https://wiki.cs.auckland.ac.nz/stageonewiki/index.php?title=List_of_Intel_CPU_microarchitectures&amp;diff=38502"/>
		<updated>2015-08-02T11:32:29Z</updated>

		<summary type="html">&lt;p&gt;Jwu550: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;=List of Intel CPU microarchitectures=&lt;br /&gt;
&#039;&#039;&#039;The following is a partial list of Intel CPU microarchitectures. The list is not complete.&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
===x86 microarchitectures===&lt;br /&gt;
*8086: first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80.&lt;br /&gt;
*186: included a DMA controller, interrupt controller, timers, and chip select logic.&lt;br /&gt;
*286: first x86 processor with protected mode&lt;br /&gt;
*i386: first 32-bit x86 processor&lt;br /&gt;
*i486: Intel&#039;s second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining.&lt;br /&gt;
*P5: original Pentium microprocessors&lt;br /&gt;
*P6: used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. Pentium M: updated version of Pentium III&#039;s P6 microarchitecture designed from the ground up for mobile computing.&lt;br /&gt;
*Enhanced Pentium M: updated, dual core version of the Pentium M microarchitecture used in Core microprocessors.&lt;br /&gt;
 &lt;br /&gt;
*NetBurst: used in Pentium 4, Pentium D, and some Xeon microprocessors. Commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Later revisions were the first to feature Intel&#039;s x86-64 architecture.&lt;br /&gt;
*Core: reengineered P6-based microarchitecture used in Core 2 and Xeon microprocessors, built on a 65 nm process. Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, and SSE4.1 instructions.&lt;br /&gt;
 &lt;br /&gt;
*Nehalem: released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.&lt;br /&gt;
 &lt;br /&gt;
*Sandy Bridge: released January 9, 2011, built on a 32 nm process and used in the Core i7, Core i5, Core i3 second generation microprocessors, and in Pentium B9XX and Celeron B8XX series. Formerly called Gesher but renamed in 2007.[1] Ivy Bridge: 22 nm shrink of the Sandy Bridge microarchitecture released April 28, 2012.&lt;br /&gt;
 &lt;br /&gt;
*Haswell: new 22 nm microarchitecture, released June 3, 2013. Broadwell: 14 nm shrink of the Haswell microarchitecture, released in September 2014. Formerly called Rockwell.&lt;br /&gt;
 &lt;br /&gt;
*Skylake: future Intel microarchitecture, based on a 14 nm process. Kaby Lake: expected in 2016&lt;br /&gt;
*Cannonlake: 10 nm shrink of the Skylake microarchitecture. Formerly called Skymont.&lt;br /&gt;
 &lt;br /&gt;
*Larrabee: multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called MIC (Many Integrated Core).&lt;br /&gt;
*Bonnell: 45 nm, low-power, in-order microarchitecture for use in Atom processors. Saltwell: 32 nm shrink of the Bonnell microarchitecture.&lt;br /&gt;
 &lt;br /&gt;
*Silvermont: 22 nm, out-of-order microarchitecture for use in Atom processors. Airmont: 14 nm shrink of the Silvermont microarchitecture.&lt;br /&gt;
 &lt;br /&gt;
*Goldmont: 14 nm Atom microarchitecture.&lt;/div&gt;</summary>
		<author><name>Jwu550</name></author>
	</entry>
	<entry>
		<id>https://wiki.cs.auckland.ac.nz/stageonewiki/index.php?title=User:Jwu550&amp;diff=38501</id>
		<title>User:Jwu550</title>
		<link rel="alternate" type="text/html" href="https://wiki.cs.auckland.ac.nz/stageonewiki/index.php?title=User:Jwu550&amp;diff=38501"/>
		<updated>2015-08-02T11:22:51Z</updated>

		<summary type="html">&lt;p&gt;Jwu550: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;Welcome to the test Wiki page created by user: jwu550&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;&#039;&#039; DISCLAIMER: The following information was borrowed from Wikipedia.com for design testing purpose only. &#039;&#039;&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
= Skylake (microarchitecture) =&lt;br /&gt;
&lt;br /&gt;
Skylake is the codename used by Intel for a processor microarchitecture under development and due to launch in 2015 as the successor to the Broadwell microarchitecture.Skylake is a microarchitecture redesign using an already existing process technology, serving as a &amp;quot;tock&amp;quot; in the Intel&#039;s &amp;quot;tick-tock&amp;quot; manufacturing and design model. According to Intel, the redesign brings greater CPU and GPU performance and reduced power consumption. Skylake will use the same 14 nm manufacturing process as Broadwell despite the expectancy of the manufacturing process&#039; transition to 10 nm in 2017 following the Skylake&#039;s &amp;quot;tick&amp;quot; step in the tick-tock release cycle; the codename for this 10 nm die shrink is Cannonlake.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Features ==&lt;br /&gt;
&lt;br /&gt;
Like its predecessor, Broadwell, Skylake is expected to become initially available in four variants, identified by the suffixes &amp;quot;S&amp;quot; (SKL-S), &amp;quot;H&amp;quot; (SKL-H), &amp;quot;U&amp;quot; (SKL-U), and &amp;quot;Y&amp;quot; (SKL-Y). An overclockable &amp;quot;K&amp;quot; variant with unlocked multipliers is expected to launch at the same time. The H, U and Y variants will be manufactured in ball grid array (BGA) packaging, while the S variant will be manufactured in land grid array (LGA) packaging using a new socket, LGA 1151. Skylake will be used in conjunction with Intel 100 Series chipsets, also known as Sunrise Point.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
=== Architecture ===&lt;br /&gt;
*14 nm manufacturing process&lt;br /&gt;
*LGA 1151 socket&lt;br /&gt;
*Z170/H170 chipset (Sunrise Point)&lt;br /&gt;
*Thermal design power (TDP) up to 95 W (LGA 1151)&lt;br /&gt;
*Support for both DDR3 SDRAM and DDR4 SDRAM in mainstream variants, using custom UniDIMM SO-DIMM form factor with up to 64 GB of RAM on LGA 1151 variants.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
==== See also ====&lt;br /&gt;
#[[List of Intel CPU microarchitectures |List of Intel CPU microarchitectures]]&lt;br /&gt;
#[https://en.wikipedia.org/wiki/DDR3_SDRAM DDR3 SDRAM]&lt;br /&gt;
#[https://en.wikipedia.org/wiki/DDR4_SDRAM DDR4 SDRAM]&lt;/div&gt;</summary>
		<author><name>Jwu550</name></author>
	</entry>
	<entry>
		<id>https://wiki.cs.auckland.ac.nz/stageonewiki/index.php?title=User:Jwu550&amp;diff=38500</id>
		<title>User:Jwu550</title>
		<link rel="alternate" type="text/html" href="https://wiki.cs.auckland.ac.nz/stageonewiki/index.php?title=User:Jwu550&amp;diff=38500"/>
		<updated>2015-08-02T11:16:03Z</updated>

		<summary type="html">&lt;p&gt;Jwu550: 2nd Revision&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;Welcome to the test Wiki page created by user: jwu550&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;&#039;&#039; DISCLAIMER: The following information was borrowed from Wikipedia.com for design testing purpose only. &#039;&#039;&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
= Skylake (microarchitecture) =&lt;br /&gt;
&lt;br /&gt;
Skylake is the codename used by Intel for a processor microarchitecture under development and due to launch in 2015 as the successor to the Broadwell microarchitecture.Skylake is a microarchitecture redesign using an already existing process technology, serving as a &amp;quot;tock&amp;quot; in the Intel&#039;s &amp;quot;tick-tock&amp;quot; manufacturing and design model. According to Intel, the redesign brings greater CPU and GPU performance and reduced power consumption. Skylake will use the same 14 nm manufacturing process as Broadwell despite the expectancy of the manufacturing process&#039; transition to 10 nm in 2017 following the Skylake&#039;s &amp;quot;tick&amp;quot; step in the tick-tock release cycle; the codename for this 10 nm die shrink is Cannonlake.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Features ==&lt;br /&gt;
&lt;br /&gt;
Like its predecessor, Broadwell, Skylake is expected to become initially available in four variants, identified by the suffixes &amp;quot;S&amp;quot; (SKL-S), &amp;quot;H&amp;quot; (SKL-H), &amp;quot;U&amp;quot; (SKL-U), and &amp;quot;Y&amp;quot; (SKL-Y). An overclockable &amp;quot;K&amp;quot; variant with unlocked multipliers is expected to launch at the same time. The H, U and Y variants will be manufactured in ball grid array (BGA) packaging, while the S variant will be manufactured in land grid array (LGA) packaging using a new socket, LGA 1151. Skylake will be used in conjunction with Intel 100 Series chipsets, also known as Sunrise Point.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
=== Architecture ===&lt;br /&gt;
*14 nm manufacturing process&lt;br /&gt;
*LGA 1151 socket&lt;br /&gt;
*Z170/H170 chipset (Sunrise Point)&lt;br /&gt;
*Thermal design power (TDP) up to 95 W (LGA 1151)&lt;br /&gt;
*Support for both DDR3 SDRAM and DDR4 SDRAM in mainstream variants, using custom UniDIMM SO-DIMM form factor with up to 64 GB of RAM on LGA 1151 variants.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
==== See also ====&lt;br /&gt;
*[[List of Intel CPU microarchitectures |List of Intel CPU microarchitectures]]&lt;/div&gt;</summary>
		<author><name>Jwu550</name></author>
	</entry>
	<entry>
		<id>https://wiki.cs.auckland.ac.nz/stageonewiki/index.php?title=User:Jwu550&amp;diff=38499</id>
		<title>User:Jwu550</title>
		<link rel="alternate" type="text/html" href="https://wiki.cs.auckland.ac.nz/stageonewiki/index.php?title=User:Jwu550&amp;diff=38499"/>
		<updated>2015-08-02T10:48:05Z</updated>

		<summary type="html">&lt;p&gt;Jwu550: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;&#039;&#039;&#039;User:Jwu550&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
This is the user page for Jiaming Wu and it is the first page created by this student.&lt;/div&gt;</summary>
		<author><name>Jwu550</name></author>
	</entry>
</feed>